As electronic circuits continue to become smaller and are widely applied in unprotected environments, it has become easier to either completely destroy or otherwise impair electronic components therein by application of voltages beyond component ratings. In particular, many integrated circuits and semiconductor devices are highly susceptible to damage from the unintended discharge of static electricity, generally as a result of handling or from physical contact with another charged body, or from electrical overstress. Electrostatic discharge is the transfer of an electric charge between bodies at different electrostatic potentials (voltages), caused by direct contact, or induced by an electrostatic field. Electrical overstress generally refers to the occurrence of a transient voltage in a circuit above its rated operating voltage. These events have become a critical problem for the electronics industry.
Device failures that result from ESD or EOS events are not always immediately catastrophic or apparent. Often, the device is only slightly weakened but is less able to withstand normal operating stresses and, hence, may result in a reliability problem. Therefore, various ESD and EOS protection circuits should be included in the device to protect its various components.
When an ESD discharge or EOS event is coupled to a transistor or other semiconductor element, the high voltage and current of the ESD pulse or EOS event relative to the voltage- and current-sustaining capabilities of structures within the device can break down the transistor, and potentially cause immediate or latent damage. Consequently, circuits associated with input/output pads of an integrated circuit require protection from an ESD pulse and an EOS event so that they are not damaged by such occurrences.
TLP (transmission line pulsing) data of ESD (electro-static discharge) protection devices in various semiconductor technologies show an inhibited avalanche breakdown phenomenon during the duration of a short ESD pulse (˜100 ns). The voltage developed across the devices during an ESD pulse can reach values which are 10-15 volts higher than measured dc breakdown voltages, i.e., measured breakdown voltages applied for longer intervals of time. For example, a device exposed to a short-duration ESD pulse can exhibit a peak breakdown voltage of 45 volts, whereas a longer duration ESD pulse may exhibit a breakdown voltage of only 28 volts for the same device.
ESD protection devices are designed to carry a high current while clamping the voltage below the destruction voltages of functional devices and circuits during ESD pulses. The occurrence of voltages higher than the originally intended value can lead to ESD failures within the functional circuitry.
ESD devices exhibiting such inhibited breakdown phenomena may show a tendency to failure during ISO (International Organization for Standardization) short test pulses, which are frequently used for qualification of automotive and industrial products.
Thus, there is a need for ESD/EOS protection devices capable of fast turn-on of avalanche breakdown under ESD, EOS, and ISO test pulse conditions, thereby preventing failure of circuits and products using these devices for ESD protection.